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19-3542; Rev 0; 2/05
KIT ATION EVALU E AILABL AV
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs
General Description
The MAX5891 advanced 16-bit, 600Msps, digital-toanalog converter (DAC) meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from +3.3V and +1.8V supplies, the MAX5891 DAC supports update rates of 600Msps using high-speed LVDS inputs while consuming only 298mW of power and offers exceptional dynamic performance such as 80dBc spurious-free dynamic range (SFDR) at fOUT = 30MHz. The MAX5891 utilizes a current-steering architecture that supports a 2mA to 20mA full-scale output current range, and produces -2dBm to -22dBm full-scale output signal levels with a double-terminated 50 load. The MAX5891 features an integrated +1.2V bandgap reference and control amplifier to ensure high-accuracy and low-noise performance. A separate reference input (REFIO) allows for the use of an external reference source for optimum flexibility and improved gain accuracy. The MAX5891 digital inputs accept LVDS voltage levels, and the flexible clock input can be driven differentially or single-ended, AC- or DC-coupled. The MAX5891 is available in a 68-pin QFN package with an exposed paddle (EP) and is specified for the extended (-40C to +85C) temperature range. Refer to the MAX5890* and MAX5889* data sheets for pin-compatible 14-bit and 12-bit versions of the MAX5891. 600Msps Output Update Rate Low Noise Spectral Density: -163dBFS/Hz at fOUT = 36MHz Excellent SFDR and IMD Performance SFDR = 80dBc at fOUT = 30MHz (to Nyquist) SFDR = 69dBc at fOUT = 130MHz (to Nyquist) IMD = -94dBc at fOUT = 30MHz IMD = -77dBc at fOUT = 130MHz ACLR = 73dB at fOUT = 122.88MHz 2mA to 20mA Full-Scale Output Current LVDS-Compatible Digital Inputs On-Chip +1.2V Bandgap Reference Low 298mW Power Dissipation at 600Msps Compact (10mm x 10mm) QFN-EP Package Evaluation Kit Available (MAX5891EVKIT)
Features
MAX5891
Ordering Information
PART TEMP RANGE PIN-PACKAGE 68 QFN-EP** PKG CODE G6800-4
MAX5891EGK -40C to +85C **EP = Exposed paddle.
Functional Diagram
MAX5891
OUTP D0-D15 LVDS DATA INPUTS
Applications
Base Stations: Single/Multicarrier UMTS, CDMA, GSM Communications: Fixed Broadband Wireless Access, Point-to-Point Microwave Direct Digital Synthesis (DDS) Cable Modem Termination Systems (CMTS) Automated Test Equipment (ATE) Instrumentation
+1.2V REFERENCE DACREF REFIO FSADJ
LVDS RECEIVER
LATCH
600MHz 16-BIT DAC OUTN
Selector Guide
PART MAX5889* MAX5890* RESOLUTION (BITS) 12 14 UPDATE RATE LOGIC INPUT (Msps) 600 600 LVDS LVDS LVDS
CLKP CLKN
CLK INTERFACE POWER DOWN PD
MAX5891 16 600 *Future product--contact factory for availability.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
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16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs MAX5891
ABSOLUTE MAXIMUM RATINGS
AVDD1.8, DVDD1.8 to AGND, DGND, DACREF, and CGND.......................................................-0.3V to +2.16V AVDD3.3, DVDD3.3, AVCLK to AGND, DGND, DACREF, and CGND.........................................-0.3V to +3.9V REFIO, FSADJ to AGND, DACREF, DGND, and CGND ..........................-0.3V to (AVDD3.3 + 0.3V) OUTP, OUTN to AGND, DGND, DACREF, and CGND .......................................-1.2V to (AVDD3.3 + 0.3V) CLKP, CLKN to AGND, DGND, DACREF, and CGND..........................................-0.3V to (AVCLK + 0.3V) PD to AGND, DGND, DACREF, and CGND.......................................-0.3V to (DVDD3.3 + 0.3V) Digital Data Inputs (D0N-D15N, D0P-D15P) to AGND, DGND, DACREF, and CGND ..........-0.3V to (DVDD1.8 + 0.3V) Continuous Power Dissipation (TA = +70C) (Note 1) 68-Pin QFN-EP (derate 28.6mW/C above +70C)....3333mW Thermal Resistance JA (Note 1) ....................................24C/W Operating Temperature Range ..........................-40C to +85C Junction Temperature .....................................................+150C Storage Temperature Range ............................-60C to +150C Lead Temperature (soldering, 10s) ................................+300C
Note 1: Thermal resistance based on a multilayer board with 4x4 via array in exposed paddle area
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference VREFIO = +1.2V, output load 50 double-terminated, transformer-coupled output, IOUT = 20mA, TA = -40C to +85C, unless otherwise noted. Specifications at TA +25C are guaranteed by production testing. Specifications at TA < +25C are guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full-Scale Gain Error Gain-Drift Tempco Full-Scale Output Current Output Compliance Output Resistance Output Capacitance Output Leakage Current DYNAMIC PERFORMANCE Maximum DAC Update Rate Minimum DAC Update Rate fCLK = 500MHz, -12dBFS, 20MHz offset from the carrier fCLK = 500MHz, 0dBFS fOUT = 36MHz AFULL-SCALE = -3.5dBm fOUT = 151MHz AFULL-SCALE = -6.4dBm fOUT = 36MHz fOUT = 151MHz 600 1 -163 dBFS/Hz -155 70 64 dB Msps Msps ROUT COUT PD = high, power-down mode IOUT Single-ended INL DNL OS GEFS External reference Internal reference External reference 2 -1.0 1 5 1 Measured differentially Measured differentially -0.02 -4 16 3.8 1.6 0.001 1 130 100 20 +1.1 +0.02 +4 Bits LSB LSB %FS %FS ppm/C mA V M pF A SYMBOL CONDITIONS MIN TYP MAX UNITS
Noise Spectral Density
N
Signal-to-Noise Ratio Over Nyquist
SNR
2
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16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference VREFIO = +1.2V, output load 50 double-terminated, transformer-coupled output, IOUT = 20mA, TA = -40C to +85C, unless otherwise noted. Specifications at TA +25C are guaranteed by production testing. Specifications at TA < +25C are guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS fCLK = 200MHz, 0dBFS Spurious-Free Dynamic Range to Nyquist fCLK = 200MHz, -12dBFS SFDR fCLK = 500MHz, 0dBFS fOUT = 16MHz fOUT = 30MHz fOUT = 16MHz fOUT = 30MHz fOUT = 16MHz fOUT = 30MHz fOUT = 130MHz fOUT = 200MHz fCLK = 500MHz Two-Tone IMD TTIMD fCLK = 500MHz fOUT1 = 29MHz, fOUT2 = 30MHz, -6.5dBFS per tone fOUT1 = 129MHz, fOUT2 = 130MHz, -6.5dBFS per tone fCLK = 491.52MHz, fOUT = 30.72MHz fCLK = 491.52MHz, fOUT = 122.88MHz fCLK = 491.52MHz, fOUT = 30.72MHz fCLK = 491.52MHz, fOUT = 122.88MHz Output Bandwidth REFERENCE Internal Reference Voltage Range Reference Input Voltage Range Reference Input Resistance Reference Voltage Temperature Drift VREFIO VREFIOCR RREFIO TCOREF Using external reference 1.14 0.10 1.2 1.2 10 50 1.26 1.32 V V k ppm/C BW-1dB (Note 2) 77 MIN TYP 86 84 76 76 84 80 69 63 -94 dBc -77 dBc MAX UNITS
MAX5891
82 73 dB 74 67 1000 MHz
WCDMA single carrier Adjacent Channel Leakage Power Ratio ACLR WCDMA four carriers
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3
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs MAX5891
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference VREFIO = +1.2V, output load 50 double-terminated, transformer-coupled output, IOUT = 20mA, TA = -40C to +85C, unless otherwise noted. Specifications at TA +25C are guaranteed by production testing. Specifications at TA < +25C are guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Output Fall Time Output Rise Time Output Propagation Delay Output Settling Time Glitch Impulse Output Noise TIMING CHARACTERISTICS Input Data Rate Data Latency Data to Clock Setup Time Data to Clock Hold Time Clock Frequency Minimum Clock Pulse-Width High Minimum Clock Pulse-Width Low Turn-On Time CMOS LOGIC INPUT (PD) Input Logic High Input Logic Low Input Current Input Capacitance LVDS INPUTS Differential Input High Differential Input Low Common-Mode Voltage Range Differential Input Resistance Common-Mode Input Resistance Input Capacitance Clock Common-Mode Voltage Minimum Differential Input Voltage Swing VIHLVDS VILLVDS VICMLVDS RIDLVDS RICMLVDS CINLVDS CLKP and CLKN are internally biased 1.125 110 3.2 3 AVCLK / 2 0.5 +100 -100 1.375 mV mV V k pF V VP-P VIH VIL IIN CIN -5 1.8 3 0.7 x DVDD3.3 0.3 x DVDD3.3 +5 V V A pF tSETUP tHOLD fCLK tCH tCL tSHDN Referenced to rising edge of clock (Note 4) Referenced to rising edge of clock (Note 4) CLKP, CLKN CLKP, CLKN CLKP, CLKN External reference, PD falling edge to output settle within 1% 0.6 0.6 350 -1.2 2 600 5.5 600 MWps Clock cycles ns ns MHz ns ns s NOUT SYMBOL tFALL tRISE tPD CONDITIONS 90% to 10% (Note 3) 10% to 90% (Note 3) Reference to data latency (Note 3) To 0.025% of the final value (Note 3) Measured differentially IOUT = 2mA IOUT = 20mA MIN TYP 0.4 0.4 2.5 11 1 30 30 MAX UNITS ns ns ns ns pV*s pA/Hz
ANALOG OUTPUT TIMING (Figure 3)
DIFFERENTIAL CLOCK INPUTS (CLKP, CLKN)
4
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16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference VREFIO = +1.2V, output load 50 double-terminated, transformer-coupled output, IOUT = 20mA, TA = -40C to +85C, unless otherwise noted. Specifications at TA +25C are guaranteed by production testing. Specifications at TA < +25C are guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Minimum Common-Mode Voltage Maximum Common-Mode Voltage Input Resistance Input Capacitance POWER SUPPLIES Analog Supply Voltage Range Clock Supply Voltage Range Digital Supply Voltage Range AVDD3.3 AVDD1.8 AVCLK DVDD3.3 DVDD1.8 fCLK = 100MHz, fOUT = 16MHz IAVDD3.3 Analog Supply Current IAVDD1.8 fCLK = 500MHz, fOUT = 16MHz fCLK = 600MHz, fOUT = 16MHz fCLK = 100MHz, fOUT = 16MHz fCLK = 500MHz, fOUT = 16MHz fCLK = 600MHz, fOUT = 16MHz fCLK = 100MHz, fOUT = 16MHz Clock Supply Current IAVCLK fCLK = 500MHz, fOUT = 16MHz fCLK = 600MHz, fOUT = 16MHz fCLK = 100MHz, fOUT = 16MHz IDVDD3.3 Digital Supply Current IDVDD1.8 fCLK = 500MHz, fOUT = 16MHz fCLK = 600MHz, fOUT = 16MHz fCLK = 100MHz, fOUT = 16MHz fCLK = 500MHz, fOUT = 16MHz fCLK = 600MHz, fOUT = 16MHz fCLK = 100MHz, fOUT = 16MHz fCLK = 500MHz, fOUT = 16MHz Total Power Dissipation PDISS fCLK = 600MHz, fOUT = 16MHz Power-down, clock static low, data input static Power-Supply Rejection Ratio PSRR (Note 5) 3.135 1.710 3.135 3.135 1.710 3.3 1.8 3.3 3.3 1.8 26.5 26.5 26.5 11.3 50 61 2.8 2.8 2.8 0.2 0.2 0.2 10.6 44 50.5 137 267 298 13 0.025 W %FS 301 mW 50 0.5 mA 3.6 mA 58 28 mA 3.465 1.890 3.465 3.465 1.890 V V V RCLK CCLK Single-ended SYMBOL CONDITIONS MIN TYP 1 1.9 5 3 MAX UNITS V V k pF
MAX5891
Note 2: Note 3: Note 4: Note 5:
This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5891. Parameter measured single-ended with 50 double-terminated outputs. Not production tested. Guaranteed by design. Parameter defined as the change in midscale output caused by a 5% variation in the nominal supply voltages.
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5
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs MAX5891
Typical Operating Characteristics
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference VREFIO = +1.2V, output load 50 double-terminated, transformer-coupled output, IOUT = 20mA, TA = +25C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 100MHz)
MAX5891 toc01
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 200MHz)
MAX5891 toc02
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 500MHz)
90 80 70 SFDR (dBc) 0dBFS
MAX5891 toc03
100 90 80 70 SFDR (dBc) 60 50 40 30 20 10 0 0 10 20 30 0dBFS -6dBFS -12dBFS
100 90 80 70 SFDR (dBc) 60 50 40 30 20 10 0 0dBFS -6dBFS -12dBFS
100
60 50 40 30 20 10 0 -6dBFS -12dBFS
40
0
10
20
30
40
50
60
70
80
0
40
80
120
160
200
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 600MHz)
MAX5891 toc04
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 500MHz, IOUT = 20mA, 10mA, 5mA)
90 80 70 SFDR (dBc) 60 50 40 30 20 10 0 5mA 10mA 20mA
MAX5891 toc05
DAC OUTPUT SPECTRAL PLOT (fCLK = 200MHz)
-10 -20 OUTPUT POWER (dBm) -30 -40 -50 -60 -70 -80 -90 -100
MAX5891 toc06
100 90 80 70 SFDR (dBc) 60 50 40 30 20 10 0 0 40 80 120 160 -6dBFS -12dBFS 0dBFS
100
0
200
0
40
80
120
160
200
0
10 20 30 40 50 60 70 80 90 100 OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
DAC OUTPUT SPECTRAL PLOT (fCLK = 500MHz)
MAX5891 toc07
TWO-TONE SPECTRAL PLOT (fCLK = 500MHz, -6.5dBFS PER TONE)
MAX5891 toc08
TWO-TONE SPECTRAL PLOT (fCLK = 500MHz, -6.5dBFS PER TONE)
-10 -20 OUTPUT POWER (dBm) -30 -40 -50 -60 -70 -80 -90
MAX5891 toc09
0 -10 OUTPUT POWER (dBm) -20 -30 -40 -50 -60 -70 -80 -90 0 50 100 150 200
0 -10 -20 OUTPUT POWER (dBm) -30 -40 -50 -60 -70 -80 -90 -100
0
250
127
128
129
130
131
132
-100 27 28 29 30 31 32 OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
6
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16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs MAX5891
Typical Operating Characteristics (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference VREFIO = +1.2V, output load 50 double-terminated, transformer-coupled output, IOUT = 20mA, TA = +25C, unless otherwise noted.)
TWO-TONE INTERMODULATION DISTORTION vs. OUTPUT FREQUENCY (fCLK = 500MHz, 1MHz CARRRIER SPACING)
MAX5891 toc10
SINGLE-CARRIER WCDMA ACLR (fCLK = 491.52MHz)
MAX5891 toc11
FOUR-CARRIER WCDMA ACLR (fCLK = 491.52MHz)
-30 -40 OUTPUT POWER (dBm) -50 -60 -70 -80 -90 -100 -110 -120 -130 ACLR = 67.3dB fCENTER = 122.88MHz
MAX5891 toc12
-60 -70 -6.5dBFS -80 SFDR (dBc) -90 -100 -110 -120 0 40 80 120 160 -12dBFS
-20 -30 -40 OUTPUT POWER (dBm) -50 -60 -70 -80 -90 -100 -110 -120 -130
ACLR = 72.3dB fCENTER = 122.88MHz
-20
200
2.5MHz/div
4.06MHz/div
OUTPUT FREQUENCY (MHz)
SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE (fCLK = 500MHz)
MAX5891 toc13
INTEGRAL NONLINEARITY
3 2 0
MAX5891 toc14
DIFFERENTIAL NONLINEARITY
MAX5891 toc15
100 fOUT = 10MHz
4
2 1
90
SFDR (dBc)
INL (LSB)
80
fOUT = 50MHz
DNL (LSB)
1 0 -1
-1 -2 -3
70 fOUT = 100MHz 60
-2 -3
50 -40 -15 10 35 60 85 TEMPERATURE (C)
-4 0 8192 16384 24576 32768 40960 49152 57344 65536
-4 0 8192 16384 24576 32768 40960 49152 57344 65536
DIGITAL INPUT CODE
DIGITAL INPUT CODE
TOTAL POWER DISSIPATION vs. CLOCK FREQUENCY (fOUT = 16MHz, AOUT = 0dBFS)
MAX5891 toc16
350 300 POWER DISSIPATION (mW) 250 200 150 100 50 0 0 100 200 300 400 500
600
CLOCK FREQUENCY (MHz)
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16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs MAX5891
Pin Description
PIN 1, 3, 5, 7, 9, 46, 48, 50, 52, 54, 56, 58, 60, 63, 65, 67 2, 4, 6, 8, 45, 47, 49, 51, 53, 55, 57, 59, 62, 64, 66, 68 10 15, 20, 23, 24, 27, 30, 33 11 12 13, 42, 43, 44 14, 21, 22, 25, 26, 31, 32 16 NAME FUNCTION D4N, D3N, D2N, D1N, D0N, D15N, D14N, D13N, D12N, Differential Negative LVDS Inputs. Data bits D0-D15 (offset binary format). D11N, D10N, D9N, D8N, D7N, D6N, D5N D3P, D2P, D1P, D0P, D15P, D14P, D13P, D12P, D11P, D10P, D9P, D8P, D7P, D6P, D5P, D4P DGND AGND DVDD3.3 PD N.C. AVDD3.3 REFIO
Differential Positive LVDS Inputs. Data bits D0-D15 (offset binary format).
Digital Ground. Ground return for DVDD3.3 and DVDD1.8. Analog Ground. Ground return for AVDD3.3 and AVDD1.8. Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1F capacitor to DGND. Power-Down Input. Set PD high to force the DAC into power-down mode. Set PD low for normal operation. PD has an internal 2A pulldown. No Connection. Leave floating or connect to AGND. Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1F capacitor to AGND. Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 0.1F capacitor to AGND. REFIO can be driven with an external reference source. Full-Scale Current Adjustment. Connect an external resistor RSET between FSADJ and DACREF to set the output full-scale current. The output full-scale current is equal to 32 x VREF / RSET. Current-Set Resistor Return Path. Internally connected to ground, but do not use as ground connection. Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a 0.1F capacitor to AGND. Complementary DAC Output. Negative terminal for current output. DAC Output. Positive terminal for current output. Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1F capacitor to CGND. Clock Supply Ground Complementary Converter Clock Input. Negative input terminal for differential converter clock. Converter Clock Input. Positive input terminal for differential converter clock. Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a 0.1F capacitor to DGND. Exposed Pad. Must be connected to common point for AGND, DGND, and CGND through a low-impedance path. EP is internally connected to AGND, DGND, and CGND.
17
FSADJ
18 19, 34, 35 28 29 36, 41 37, 40 38 39 61 --
DACREF AVDD1.8 OUTN OUTP AVCLK CGND CLKN CLKP DVDD1.8 EP
8
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16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs
Detailed Description
Architecture
The MAX5891 high-performance, 16-bit, current-steering DAC (see the Functional Diagram) operates with DAC update rates up to 600Msps. The current-steering array generates differential full-scale currents in the 2mA to 20mA range. An internal current-switching network, in combination with external 50 termination resistors, converts the differential output currents into a differential output voltage with a 0.1V to 1V peak-topeak output voltage range. The analog outputs have a -1.0V to +1.1V voltage compliance. For applications requiring high dynamic performance, use the differential output configuration and limit the output voltage swing to 0.5V at each output. An integrated +1.2V bandgap reference, control amplifier, and user-selectable external resistor determine the data converter's full-scale output range.
MAX5891
Table 1. IOUTFS and RSET Selection Matrix Based on a Typical +1.200V Reference Voltage
FULL-SCALE CURRENT IOUTFS (mA) 2 5 10 15 20 RSET () CALCULATED 19.2k 7.68k 3.84k 2.56k 1.92k 1% EIA STD 19.1k 7.5k 3.83k 2.55k 1.91k
+1.2V REFERENCE
10k REFIO 0.1F OUTP FSADJ IREF RSET DACREF IREF = VREFIO / RSET CURRENT-SOURCE ARRAY DAC OUTN
Reference Architecture and Operation
The MAX5891 operates with the internal +1.2V bandgap reference or an external reference voltage source. REFIO serves as the input for an external, lowimpedance reference source or as a reference output when the DAC operates in internal reference mode. For stable operation with the internal reference, bypass REFIO to AGND with a 0.1F capacitor. The REFIO output resistance is 10k. Buffer REFIO with a high-inputimpedance amplifier when using it as a reference source for external circuitry. The MAX5891's reference circuit (Figure 1) employs a control amplifier to regulate the full-scale current, IOUTFS, for the differential current outputs of the DAC. Calculate the output current as follows: IOUTFS = 32 x VREFIO RSET 1 x 1 - 216
Figure 1. Reference Architecture, Internal Reference Configuration
Analog Outputs (OUTP, OUTN)
The complementary current outputs (OUTP, OUTN) can be connected in a single-ended or differential configuration. A load resistor converts these two output currents into complementary single-ended output voltages. A transformer or a differential amplifier converts the differential voltage existing between OUTP and OUTN to a single-ended voltage. When not using a transformer, terminate each output with a 25 resistor to ground and a 50 resistor between the outputs. To generate a single-ended output, select OUTP as the output and connect OUTN to AGND. Figure 2 shows a simplified diagram of the internal output structure of the MAX5891.
where I OUTFS is the full-scale output current of the DAC. R SET (located between FSADJ and DACREF) determines the amplifier's full-scale output current for the DAC. See Table 1 for a matrix of different IOUTFS and RSET selections.
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9
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs MAX5891
Data-Timing Relationship
AVDD3.3 CURRENT SOURCES CURRENT SWITCHES
Figure 3 shows the timing relationship between digital LVDS data, clock, and output signals. The MAX5891 features a 2ns hold, a -1.2ns setup, and a 2.5ns propagation delay time. There is a 5.5 clock-cycle latency between data write operation and the corresponding analog output transition.
LVDS Data Inputs
IOUT OUTN OUTP IOUT
The MAX5891 has 16 pairs of LVDS data inputs (offset binary format) and can accept data rates up to 600MWps. Each differential input pair is terminated with an internal 110 resistor. The common-mode input resistance is 3.2k.
Figure 2. Simplified Analog Output Structure
Power-Down Operation (PD)
The MAX5891 features a power-down mode that reduces the DAC's power consumption. Set PD high to power down the MAX5891. Set PD low or leave unconnected for normal operation. When powered down, the MAX5891 overall power consumption is reduced to less than 13W. The MAX5891 requires 350s to wake up from power-down and enter a fully operational state if the external reference is used. If the internal reference is used, the power-down recovery time is 10ms. The PD internal pulldown circuit sets the MAX5891 in normal mode when PD is left unconnected.
Clock Inputs (CLKP, CLKN)
To achieve the best possible jitter performance, the MAX5891 features flexible differential clock inputs (CLKP, CLKN) that operate from a separate clock power supply (AV CLK ). Drive the differential clock inputs from a single-ended or a differential clock source. For highest dynamic performance, differential clock source is required. For single-ended operation, drive CLKP with a logic source and bypass CLKN to CGND with a 0.1F capacitor. CLKP and CLKN are internally biased at AVCLK / 2, allowing the AC-coupling of clock sources directly to the device without external resistors to define the DC level. The input resistance from CLKP and CLKN to ground is approximately 5k.
CLKP
CLKN
D0-D16 tSETUP IOUTP
DN
DN + 1
DN + 2 tHOLD
DN + 3
DN + 4
DN + 5
DN + 6
DN + 7
OUTN - 7 IOUTN
OUTN - 6
OUTN - 5
OUTN - 4
OUTN - 3
OUTN - 2
OUTN-1
OUTN
tPD
Figure 3. Timing Relationship Between Clock, Input Data, and Analog Output 10 ______________________________________________________________________________________
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs
Applications Information
Clock Interface
To achieve the best possible jitter performance, the MAX5891 features flexible differential clock inputs (CLKP, CLKN) that operate from a separate clock power supply (AVCLK). Use a low-jitter clock to reduce the DAC's phase noise and wideband noise. To achieve the best DAC dynamic performance, the CLKP/CLKN input source must be designed carefully. The differential clock (CLKN and CLKP) input can be driven from a single-ended or a differential clock source. Use differential clock drive to achieve the best dynamic performance from the DAC. For single-ended operation, drive CLKP with a low noise source and bypass CLKN to CGND with a 0.1F capacitor. Figure 4 shows a convenient and quick way of applying a differential signal created from a single-ended source using a wideband transformer. Alternatively, drive CLKP/CLKN from a CMOS-compatible clock source. Use sinewave or AC-coupled differential ECL/PECL drive for best dynamic performance.
Differential Output Coupling Using a Wideband RF Transformer
Use a pair of transformers (Figure 5) or a differential amplifier configuration to convert the differential voltage existing between OUTP and OUTN to a single-ended voltage. Optimize the dynamic performance by using a differential transformer-coupled output and limit the output power to <0dBm full scale. To achieve the best dynamic performance, use the differential transformer configuration. Terminate the DAC as shown in Figure 5, and use 50 termination at the transformer singleended output. This will provide double 50 termination for the DAC output network. With the double-terminated output and 20mA full-scale current, the DAC will produce a full-scale signal level of approximately -2dBm. Pay close attention to the transformer core saturation characteristics when selecting a transformer for the MAX5891. Transformer core saturation can introduce strong 2nd-order harmonic distortion especially at low output frequencies and high signal amplitudes. For best results, connect the center tap of the transformer to ground. When not using a transformer, terminate each DAC output to ground with a 25 resistor. Additionally, place a 50 resistor between the outputs (Figure 6). For a single-ended unipolar output, select OUTP as the output and connect OUTN to AGND. Operating the MAX5891 single-ended is not recommended because it degrades the dynamic performance. The distortion performance of the DAC depends on the load impedance. The MAX5891 is optimized for 50 differential double termination. Using higher termination impedance degrades distortion performance and increases output noise voltage.
MAX5891
WIDEBAND RF TRANSFORMER PERFORMS SINGLE-ENDED-TODIFFERENTIAL CONVERSION 25 SINGLE-ENDED CLOCK SOURCE 1:1 25
0.1F CLKP
TO DAC
0.1F CLKN
AGND
Figure 4. Differential Clock-Signal Generation
50 OUTP D0-D15 LVDS DATA INPUTS 100 T2, 1:1
VOUT, SINGLE-ENDED
MAX5891
OUTN
T1, 1:1 50
AGND
WIDEBAND RF TRANSFORMER T2 PERFORMS THE DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION
Figure 5. Differential-to-Single-Ended Conversion Using a Wideband RF Transformer ______________________________________________________________________________________ 11
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs MAX5891
25 OUTP D0-D15 LVDS DATA INPUTS 50 OUTN 25 AGND OUTP
The analog and digital power-supply inputs AV DD3.3, AVCLK, and DVDD3.3 allow a +3.135V to +3.465V supply voltage range. The analog and digital power-supply inputs AVDD1.8 and DVDD1.8 allow a +1.71V to +1.89V supply voltage range. The MAX5891 is packaged in a 68-pin QFN-EP package with exposed paddle, providing optimized DAC AC performance. The exposed pad must be soldered to the ground plane of the PC board. Thermal efficiency is not the key factor, since the MAX5891 features lowpower operation. The exposed pad ensures a solid ground connection between the DAC and the PC board's ground layer. The data converter die attaches to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows for a solid attachment of the package to the PC board with standard infrared (IR) reflow soldering techniques. A specially created land pattern on the PC board, matching the size of the EP (6mm x 6mm), ensures the proper attachment and grounding of the DAC. Place vias into the land area and implement
BYPASSING--DAC LEVEL 3.3V VOLTAGE SUPPLY
MAX5891
OUTN
Figure 6. Differential Output Configuration
Grounding, Bypassing, and Power-Supply Considerations
Grounding and power-supply decoupling strongly influence the MAX5891 performance. Unwanted digital crosstalk coupling through the input, reference, power supply, and ground connections affects dynamic performance. High-speed, high-frequency applications require closely followed proper grounding and powersupply decoupling. These techniques reduce EMI and internal crosstalk that can significantly affect the MAX5891 dynamic performance. Use a multilayer printed circuit (PC) board with separate ground and power-supply planes. Run high-speed signals on lines directly above the ground plane. Keep digital signals as far away from sensitive analog inputs and outputs, reference input sense lines, commonmode inputs, and clock inputs as practical. Use a symmetric design of clock input and the analog output lines to minimize 2nd-order harmonic distortion components, thus optimizing the DAC's dynamic performance. Keep digital signal paths short and run lengths matched to avoid propagation delay and data skew mismatches. The MAX5891 requires five separate power-supply inputs for analog (AV DD1.8 and AV DD3.3 ), digital (DVDD1.8 and DVDD3.3), and clock (AVCLK) circuitry. Decouple each AVDD3.3, AVDD1.8, AVCLK, DVDD3.3, and DVDD1.8 input with a separate 0.1F capacitor as close to the device as possible with the shortest possible connection to the respective ground plane (Figure 7). Connect all of the 3.3V supplies together at one point with ferrite beads to minimize supply noise coupling. Decouple all five power-supply voltages at the point they enter the PC board with tantalum or electrolytic capacitors. Ferrite beads with additional decoupling capacitors forming a pi network can also improve performance. Similarly, connect all 1.8V supplies together at one point with ferrite beads.
*
*
*
0.1F
0.1F
0.1F
AVDD3.3 DVDD3.3 D0-D15 LVDS DATA INPUTS
AVCLK
OUTP
MAX5891
AVDD1.8 DVDD1.8 OUTN
0.1F *FERRITE BEADS
0.1F
*
*
1.8V VOLTAGE SUPPLY
Figure 7. Recommended Power-Supply Decoupling and Bypassing Circuitry 12 ______________________________________________________________________________________
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs
large ground planes in the PC board design to ensure the highest dynamic performance of the DAC. Connect the MAX5891 exposed paddle to the common connection point of DGND, AGND, and CGND. Vias connect the top land pattern to internal or external copper planes. Use as many vias as possible to the ground plane to minimize inductance. The vias should have a diameter greater than 0.3mm.
Dynamic Performance Parameter Definitions
Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog output (RMS value) to the RMS quantization error (residual error). The ideal, theoretical maximum can be derived from the DAC's resolution (N bits): SNRdB = 6.02dB x N + 1.76dB However, noise sources such as thermal noise, reference noise, clock jitter, etc., affect the ideal reading; therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset. Noise Spectral Density The DAC output noise floor is the sum of the quantization noise and the output amplifier noise (thermal and shot noise). Noise spectral density is the noise power in 1Hz bandwidth, specified in dBFS/Hz. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal components) to the RMS value of their next-largest distortion component. SFDR is usually measured in dBc and with respect to the carrier frequency amplitude or in dBFS with respect to the DAC's full-scale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist. Two-Tone Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in dBc (or dBFS) of the worst 3rd-order IMD differential product to either output tone. The two-tone IMD performance of the MAX5891 is tested with the two individual output tone levels set to at least -6.5dBFS. Adjacent Channel Leakage Power Ratio (ACLR) Commonly used in combination with wideband codedivision multiple-access (WCDMA), ACLR reflects the leakage power ratio in dB between the measured power within a channel relative to its adjacent channel. ACLR provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited RF signal passes through a nonlinear device.
MAX5891
Static Performance Parameter Definitions
Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step height and the ideal value of 1 LSB. Offset Error The offset error is the difference between the ideal and the actual offset current. For a DAC, the offset point is the average value at the output for the two midscale digital input codes with respect to the full scale of the DAC. This error affects all codes by the same amount. Gain Error A gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the converter's specified accuracy. Glitch Impulse A glitch is generated when a DAC switches between two codes. The largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011...111 to 100...000. The glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. The glitch impluse is usually specified in pV*s.
______________________________________________________________________________________
13
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs MAX5891
Pin Configuration
DVDD1.8
D10N
D11N
68 D4N D3P D3N D2P D2N D1P D1N D0P D0N 1 2 3 4 5 6 7 8 9
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52 51 D12P 50 D13N 49 D13P 48 D14N 47 D14P 46 D15N 45 D15P 44 N.C.
MAX5891
D12N 43 N.C. 42 N.C. 41 AVCLK 40 CGND 39 CLKP 38 CLKN 37 CGND 36 AVCLK 35 AVDD1.8 34 AVDD1.8
D10P
DGND 10 DVDD3.3 11 PD 12 N.C. 13 AVDD3.3 14 AGND 15 REFIO 16 FSADJ 17 18 DACREF 19 AVDD1.8 20 AGND 21 AVDD3.3 22 AVDD3.3 23 AGND 24 AGND 25 AVDD3.3 26 AVDD3.3 27 AGND 28 OUTN 29 OUTP 30 AGND 31 AVDD3.3 32 AVDD3.3 33 AGND EXPOSED PADDLE
QFN-EP
14
______________________________________________________________________________________
D11P
D5N
D6N
D7N
D8N
D9N
D4P
D5P
D6P
D7P
D8P
D9P
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX5891
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
68L QFN.EPS

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